1. Field of the Invention
The invention relates to a method for producing a vertical semiconductor transistor component and to a vertical semiconductor transistor component.
The ever increasing packing density of circuits on semiconductor chips is placing ever greater demands on the process and circuit technology. Until now, planar MOS (Metal Oxide Semiconductor) components have been scaled by improvements in optical lithography systems. This results in a shortening of the channel length of the transistors which has the effect of enhancing performance. With a further reduction in the structure sizes, however, two main problems arise.
Firstly, the concept of the planar “bulk” MOSFET (Metal Oxide Semiconductor Field Effect Transistor) reaches its limit, since parasitic short-channel effects reduce the performance capability of this component. In this context, it has already been attempted to counteract the loss in performance by technologically complex channel doping profiles (“pockets” or “retrograde wells”). Further concepts currently being pursued to avoid parasitic short-channel effects include the production of transistors on SOI (Silicon-on-Insulator) wafers or the development of planar dual-gate transistors, in which improved gate control is achieved by embedding the channel region between two opposing gate electrodes.
The other problem is that the optical lithography systems are likely to reach their performance limits before long. An alternative scaling possibility is provided by the concept of vertical components (in contrast to planar components). With a vertical type of construction, channel lengths of below 100 nm can be readily achieved in the case of MOSFETs, since the channel length can be set with great accuracy by prescribing a layer thickness.
Published, Non-Prosecuted German Patent Application No. DE 196 32 835 A1 describes a semiconductor capacitor which has a capacitor electrode with vertical pillar structures to enlarge its capacitor area. The pillar structures are formed using a statistical mask, which permits structure sizes in the sub-100 nm range.
The article “Self-limiting oxidation for fabricating sub-5 nm silicon nanowires” by H. I. Liu, et al., Appl. Phys. Lett. 64 (11), pages 1383-1385 (1994), describes a lateral oxidation process, with which it is possible to produce vertical 2 nm wide silicon pillar structures which are surrounded by an SiO2 sheath.
In the article “Fabrication of silicon nanopillars containing polycrystalline silicon/insulator multilayer structures”, by H. Fukuda, et al., Appl. Phys. Lett. 70 (3), pages 333-335 (1997), a single-electron transistor is proposed, which includes silicon pillar structures which are produced by the lateral oxidation method described in the publication mentioned above and which, furthermore, contain a plurality of tunnel insulation layers oriented in the transverse direction with respect to the pillar axis.
In the document Patent Abstracts of Japan, vol. 1997, No. 3, JP 08306905 A, a pillar structure which is formed from a stack of semiconductor layers by a photoresist pattern is described.
In the article “Vertical MOS Transistors with 70 nm Channel Length”, by L. Risch et al., IEEE Transactions on Electron Devices, vol. 43, No. 9, pages 1495-1498, (1996), a lithographically produced vertical transistor with a channel length of 70 nm is described. A further vertical transistor with a channel length of 50 nm, which is produced by a shadow mask, is specified in the publication “Vertical Si-Metal-Oxide-Semiconductor Field Effect Transistors with Channel Lengths of 50 nm by Molecular Beam Epitaxy” by H. Gossner et al., Jpn. J. Appl. Phys. vol. 33, pages 2423-2428, (1994).
A statistical mask which is produced by applying a mixture including mask particles and spacing particles to a surface and subsequently removing the spacing particles is described in U.S. Pat. No. 5,871,870.
Published European Patent Application No. EP 0 843 361 A1, U.S. Pat. No. 5,714,766 and the publication “High-speed single-electron memory: cell design and architecture”, by H. Mizuta et al., IEEE Comput. Soc, pages 67-72, (1998), describe memory cells with pillar structures which are made with tunnel layers for the tunneling through of one or more electrons.